Device ≠ circuit
The up-to-82% SET and 54% READ energy figures reported by Das et al. concern a HfO₂/CMOS 3T1R synapse circuit. They are not measured IGZO platform savings. Source ↗
EVIDENCE-LED RESEARCH ATLAS · 2026
From material to decision. From evidence to claim.
An integrated, critical synthesis of IGZO resistive devices, analogue arrays, peripheral circuits, edge workloads, fabrication choices and system-level validation.
This is a research roadmap, not an announcement of a completed IGZO product or measured end-to-end advantage.
Explore the programme ↗
01 / CRITICAL FINDINGS
What the evidence actually says
Simulation ≠ system
Naqi et al. fabricated a 10×10 IGZO array. Their CNN/SNN recognition rates are tied to electrical and network simulation; the same article reports approximately 500 cycles and >10⁴ s retention. Source ↗
Target ≠ result
The supplied project drafts include <1 ms, <1 W, 300× and 10⁶ cycles without project-specific raw system measurements. We retain them only as hypotheses or test targets.
02 / SYSTEM ARCHITECTURE
Six coupled layers
Material & device
Film composition, electrode interface, conductance states, switching distributions, retention, endurance and read disturb.
Crossbar & 1T1R
Vector–matrix multiplication, sneak paths, line resistance, selectors and array yield.
Drivers & readout
Programming pulses, current compliance, sensing, ADC/DAC, reference cells and peripheral energy.
Hardware-aware algorithm
Measured-device-aware training, weight encoding, programming verification and recalibration.
Sensor-to-edge decision
Sensor, preprocessing, DAC/array/ADC, local inference, decision and actuation measured on a matched workload.
Secure operation & evidence
Across all layers: authorized updates, audit trails, fail-safe behavior, batch variation, uncertainty and independent replication.
Array potential becomes a system benefit only when accuracy, peripheral energy and a matched workload are measured together. Device, simulation and end-to-end results remain distinct. Jiang et al. ↗
03 / FABRICATION & ACCEPTANCE
Three routes, one acceptance standard
A · Sourced devices
Procure IGZO devices, apply incoming QC, then integrate and calibrate. The draft planning range is 18–30 months.
B1 · In-house fabrication
Record films, electrodes, lithography, annealing and batch-level metrology with traceable process revisions. Draft range: 24–36 months.
B2 · Outsourced fabrication
Control specification and provenance while retaining independent incoming QC and system integration. Draft range: 24–36 months.
All routes require prespecified pass criteria, raw traces, rejected samples, batch variation and read-disturb measurements before progressing to 32×32. Moving to 64×64 is conditional. Decision gates ↗
04 / EXPERIMENTAL VALIDATION
Measure the complete path
Device and array bench
Test state separation, write/read energy, retention, endurance, cell and batch variability, yield, MVM error and calibration cost. Compare passive crossbar with 1T1R under matched accuracy targets.
Sensor-to-decision demonstrator
Measure p50/p95/p99 latency and energy per valid inference including sensor, preprocessing, converters, array, controller and actuator. Keep a task-matched digital baseline.
E_write = ∫ V(t)I(t)dt · E_infer = E_total / N_validLock data splits, sample and batch counts, instrument bandwidth, uncertainty method, environmental conditions and failure rules before measuring.
05 / MULTIDISCIPLINARY SYNTHESIS
Six disciplines, one evidence chain
Materials science
Stoichiometry, oxygen chemistry, interfaces, process control and physical characterisation.
Electrical engineering
Line losses, selection, ADC/DAC, noise, power accounting and array scaling.
Machine learning
Hardware-aware training, quantisation, calibration, dataset leakage and matched accuracy.
Metrology
Instrument traceability, nested batch sampling, uncertainty intervals and failure reporting.
Security & safety
Authorised updates, fault injection, safe states and documented AI risk management.
Energy & economics
Energy per valid inference, idle power, process yield, maintenance and total cost boundaries.
06 / CLAIM CLASSIFICATION
Do not merge evidence levels
Measured in literature
Specific IGZO device and array results with stated structure, sample size and conditions. They are not results of the proposed platform.
Modelled
Circuit or neural-network simulation, even when parameterised with measured device data. It does not establish complete hardware performance.
Proposed
Latency, power, scaling and security goals that need preregistered tests and independent replication.
07 / INTERACTIVE FORMULATIONS
From equations to testable assumptions
Ideal crossbar
Iⱼ = Σᵢ VᵢGᵢⱼIgnores line resistance and device variation until these are added from measurement.
System energy
Eₜ = Eₛ + E_DAC + E_array + E_ADC + E_ctrlShows why an array-only value cannot support an end-to-end claim.
Simple array yield
P(all pass) = pᴺIllustrative independence assumption only; manufacturing defects can be correlated.
Normalised array error
NRMSE = √[Σ(I_meas−I_ref)² / ΣI_ref²]Show raw and post-calibration outputs separately.
Energy per valid inference
Eᵢ = ∫P_system(t)dt / N_validDeclare the measurement interval and validity rule in advance.
Tail latency
L₉₅ = Q₀.₉₅(t_decision−t_sensor)A median alone hides slow decisions.
08 / TECHNICAL LIBRARY
Download the technical reports
Evidence and materials
Device physics, metrology, fabrication gates and claim corrections, with linked primary sources.
Download report ↓Systems and benchmarking
Crossbar error budgets, end-to-end energy, fair baselines, application safety and reproducibility.
Download report ↓The complete research programme is also available as a printable page.
09 / VISUAL ATLAS
19 conceptual illustrations
These images communicate research concepts. They are not device photographs, measured plots or validated prototype results.
10 / REFERENCES
Selected primary sources and official guidance
- Naqi et al., 2024 ↗Fabricated 10×10 IGZO array; endurance and retention were measured, while classification figures have a modelling/simulation context.
- Martins et al., 2022 ↗Solution-processed IGZO devices and multilevel retention under study-specific conditions.
- Xia & Yang, 2019 ↗Review of memristive crossbar computing principles and scaling challenges.
- Jiang et al., 2026 ↗Review of accuracy strategies in analogue compute-in-memory across device, circuit and algorithm layers.
- Fu et al., 2019 ↗Piecewise-linear approaches to nonlinear synaptic weight updates; transfer to IGZO needs testing.
- Das et al., 2023 ↗HfO₂/CMOS synapse circuit preprint, not an IGZO device experiment.
- EP3588594B1 ↗Patent claims concerning a particular IGZO resistive element and programming route.
- IEA, Energy and AI, 2025 ↗Global data-centre electricity context and scenarios, not device-level performance evidence.
- MLCommons Tiny ↗Benchmark methodology for task accuracy, latency and energy of low-power inference.
- NIST AI RMF 1.0 ↗Voluntary framework for mapping, measuring and managing AI system risks.
- Printed IGZO nociceptor study, 2024 ↗Primary device study relevant to the bio-inspired threshold demonstration.